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J-Link BASE Compact Programmer

£554.40 £462.00
The J-Link line of JTAG programmers from Segger is well known for their top of the line debuggers. The J-Link BASE is a USB powered JTAG debug probe supporting a large number of CPU cores. Based on a 32-bit RISC CPU, it can communicate at high speed with the supported target CPUs. J-Link is used around the world in tens of thousand places for development and production (flash programming) purposes. The J-Link Base is a great option for those getting started with JTAG/SWD programming and debugging. Unlike the EDU Mini and the EDU this version comes with a license that allows you to build commercial products with it.
SKU
S-PGM-15347

The J-Link line of JTAG programmers from Segger is well known for their top of the line debuggers. The J-Link BASE is a USB powered JTAG debug probe supporting a large number of CPU cores. Based on a 32-bit RISC CPU, it can communicate at high speed with the supported target CPUs. J-Link is used around the world in tens of thousand places for development and production (flash programming) purposes. The J-Link Base is a great option for those getting started with JTAG/SWD programming and debugging. Unlike the EDU Mini and the EDU this version comes with a license that allows you to build commercial products with it.

With a USB port on one end, and a 20-pin JTAG connector on the other end, just plug in the included cable and connect to your favorite ARM board, or just connect the pins you need, to get started.

Includes:

  • J-Link BASE Compact Programmer
  • 0.1" 20-pin ribbon cable
  • USB cable

Features:

  • Unlimited Breakpoints
  • Free Software updates
  • Supports concurrent access to CPU by multiple applications
  • Crossplatform support (Windows, Linux, macOS)
    • Linux and Mac versions are limited to J-Link Commander, command line GDBServer, shared library (DLL equivalent)
  • Size: 47mm x 40mm x 14mm
  • Weight: 20g
  • Target Interface Voltage: 1.2V ... 5V
  • Target Supply Voltage: 5V (derived from USB voltage)
  • JTAG speed: Max 15MHz
  • SWO sampling frequency: Max 30MHz
  • Data input rise time and fall time: <=20ns
  • Data output rise time and fall time: <=10ns
  • Clock rise time and fall time: <=3ns

Documents:

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